1. Field of the Invention
This invention relates to a non-volatile random access memory (Ferroelectric RAM; FRAM) having a high load device, and more particularly to a non-volatile random access memory having a ferroelectric capacitor and a high load device.
2. Description of the Prior Art
Conventionally known typical memories capable of random access to stored data include SRAM's (static RAM's) and DRAM's (dynamic RAM's). All these conventional memories are volatile. SRAM's require six transistor devices per one memory cell so that they are limited at the degree of integration. DRAM's have the drawback that the capacitors require a periodical refreshment for holding data.
Under these circumstances, what is called FRAM's using a ferroelectric film as a capacitor are more and more noted as a non-volatile memory device capable of random access to data stored therein. Such FRAM utilizes a ferroelectric film having polarizing hysteresis property. Since polarizing charges remain even when an electric power is made OFF, the FRAM can be used as a non-volatile memory.
FIG. 10 shows a typical circuit configuration of such FRAM. As shown in FIG. 10, FRAM's basically comprise one memory cell including two transistor devices and two capacitor devices. In other words, an electrode on one side of the transistor T1 is connected to a bit line B1 while an electrode on the other side of the same transistor T1 is connected to one electrode on a transistor T2 via two capacitors C1 and C2. Furthermore, the other electrode on the transistor T2 is connected to a bit line B2. Besides, the gate electrodes on transistors T1 and T2 are connected to the same word line. A drive line is connected between the capacitors C1 and C2.
Such FRAM is written data by the polarization of one capacitor device produced by applying a high voltage or an earth voltage to the drive-line with a high voltage applied to one of the bit lines and an earth voltage applied to the other bit line. On the other hand, such FRAM is read data by detecting a difference in potential produced between one of the bit lines and the capacitor device when a high voltage is applied to the drive line with the bit lines serving as an earth potential.
However, the above FRAM requires two transistors and two capacitors per one memory cell. Thus the idea of a further increase in the memory capacity and a higher integration has produced a demand of further simplification of the device construction.
For the purpose of improving the problems, a FRAM comprising two transistors and one capacitor as shown FIG. 11(a) has been proposed.
In this type of FRAM as shown in FIGS. 11(b) and 11(c), the transistors T1 and T2 are formed on silicon substrate 51, providing four word lines 52 for one bit line 54. On both sides of the bit line 54, transistors T1 and T2 are respectively formed, sharing one of the diffused layer with each other. Each word line 52 is covered with a protective film 53. A contact pad 55 is formed on the silicon substrate 51 between the two word lines 52 in one unit cell and an interlayer insulating film 56 is formed thereon. A contact hole is formed on the contact pad 55 throughout the interlayer insulating film 56 and a contact plug 57 is embedded in the contact hole. Accumulating electrode 58 is formed on and connected to the contact plug 57, and further a ferroelectric PZT film 59 and cell plate 60 are sequentially laminated thereon, thereby forming a capacitor. Thus, a FRAM comprising two transistors T1 and T2 and one capacitor Cp can be obtained.
However, even in such a FRAM, the cell size of the unit cell in case of forming the gate electrode by 0.5 .mu.m rule is about 3.7 .mu.m.sup.2 (in FIG. 2, C:1.5.times.2.45), therefore the device is required further minimization of the cell size and high integration.
In addition, a memory cell comprising one transistor and one capacitor, which is a ferroelectric type capacitor, has been proposed.
In the foregoing section, the behavior of one memory cell of FRAM will be detailed by way of FIG. 12.
At the Time of Writing Data (Write 1 or Write 0)
Application of a potential of V.sub.cc /2 to the upper electrode of the capacitor device at the outset is followed by applying either C.sub.cc (in the case of Write 1) or 0 V (in the case of Write 0) to a bit line B1. Consequently, as shown in FIG. 12, the charge of the residual polarization each exhibiting a polarization in the reverse direction in the state of Write 1 and Write 0 is accumulated and stored in the capacitor.
At the Time of Waiting
At the time of waiting, the potential of the cell plate is set to V.sub.cc /2 while a voltage of V.sub.cc /2 is applied to the bit line, the state of polarization being kept as it is.
At the Time of Reading (Read 1 and Read 0)
The potential of the cell plate is set to V.sub.cc /2 and a voltage of V.sub.cc is applied to the bit line B1. In the case of Read 1, since the polarization is not reversed, only a current of I=(P.sub.s -P.sub.r).DELTA.t (P.sub.s designates a charge of saturated polarization, P.sub.r a charge of the residual polarization, and .DELTA.t reversion) is allowed to flow. On the other hand, in the case of Read 0, the polarization of the capacitor is reversed to provide a large variation in the charge so that a current of I={2P.sub.r +(P.sub.s -P.sub.r)}/.DELTA.t is allowed to flow. The quantity of the current allows reading data "1" and "0" with a sense amplifier.
However, in actuality, the above FRAM has a drawback that the potential on the source side (lower electrode) of the cell plate is affected by the potential V.sub.BB of the back gate on the substrate, which reverses the direction of the electric field. As a consequence, the direction of polarization is reversed, so that refreshment operation is indispensable at the time of waiting.